The present invention is in the area of CPU operations in executing instructions from software. As is known in the art there are many kinds of instruction set architectures (ISA), and certain architectures have become favored in many computer operations. One of those architectures is the well-known MIPS ISA, and the MIPS ISA is used in the present specification in several examples. The invention, however, is not limited to MIPS ISA.
One of the necessary operations in computer processes when executing instructions is moving data entities between general-purpose or cache memory and register files in a CPU where the data is readily accessible. When more than one data entity must be loaded or stored before execution can commence or continue, several instructions are needed in a conventional instruction set architecture. In applications that need to access data the present inventors have discovered that it would be desirable to have a single instruction that could load or store data entities that are related in a known pattern, and that a single instruction capable of such operation would significantly improve the speed and efficiency of many computer operations.
What is therefore clearly needed is a method and apparatus comprising a single instruction for indicating data entities having a known positional relationship in memory, and for loading or storing a series of such data entities as a result of executing the single instruction.